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Re: [charm] [ppl] Information on hierarchical load balancers


Chronological Thread 
  • From: Gengbin Zheng <gzheng AT illinois.edu>
  • To: Laércio Lima Pilla <llpilla AT inf.ufrgs.br>
  • Cc: Charm Mailing List <charm AT cs.illinois.edu>, Abhinav Bhatele <bhatele AT illinoisalumni.org>
  • Subject: Re: [charm] [ppl] Information on hierarchical load balancers
  • Date: Tue, 21 May 2013 09:20:26 -0500
  • List-archive: <http://lists.cs.uiuc.edu/pipermail/charm/>
  • List-id: CHARM parallel programming system <charm.cs.uiuc.edu>


From centralized load balancing algorithm's point of view, it does not change the PE numbering. PE always starts from 0 to maximum number of PEs in its domain.
This relative PE numbering to absolute PE numbering is done by HybridLB.

Gengbin


On Tue, May 21, 2013 at 9:09 AM, Laércio Lima Pilla <llpilla AT inf.ufrgs.br> wrote:
Thank you.

2013/5/20 Abhinav Bhatele <bhatele AT illinoisalumni.org>
tests/charm++/load_balancing/lb_test should work with src/ck-ldb/HybridLB.*

In addition, if you download NAMD (http://www.ks.uiuc.edu/Development/Download/download.cgi?PackageName=NAMD), you can look at NamdHybridLB.* under src/

- Abhinav


On Mon, May 20, 2013 at 12:27 PM, Gengbin Zheng <gzheng AT illinois.edu> wrote:

NAMD is a use case (there are some other small examples).
Hierarchical load balancer requires centralized load balancing algorithms that:

1. must use the  work() interface (instead of the strategy() interface)
2. can handle external objects that does not belong to the current processor set, e.g.  the algorithm needs to handle the case when an object in from  PE 128, while the PE set is from 0-127
3. can handle the processor's avail vector. The root processor of each processor group (or domain) is a fake processor in the sense that its availability bit is false, i.e. no object is supposed to migrate to it.

Does this change the PE numbering? 

Best regards,



Gengbin



On Mon, May 20, 2013 at 2:03 PM, Laércio Lima Pilla <llpilla AT inf.ufrgs.br> wrote:
Greetings,

I am starting to work on a hierarchical load balancer for Charm++. 
I would like to know if there is any document with information about the usage of hierarchical load balancers, and implementation requirements related to the centralized algorithms used by a hierarchical load balancer. 
The Charm++ Manual does not touch this subject. The paper entitled "Periodic Hierarchical Load Balancing for Large Supercomputers" does not go into implementation details, nor does Gengbin's thesis.

Best regards,

--
Laércio LIMA PILLA

PhD Student at 
- Federal University of Rio Grande do Sul (UFRGS) - Brazil
- University of Grenoble - France


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--
Abhinav Bhatele, people.llnl.gov/bhatele
Center for Applied Scientific Computing, Lawrence Livermore National Laboratory



--
Laércio LIMA PILLA

PhD Student at 
- Federal University of Rio Grande do Sul (UFRGS) - Brazil
- University of Grenoble - France




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