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[charm] Processor slicing and miniaturising in BigSim

From: vishwas vasudeva <vishvasu98 AT gmail.com>
To: charm AT cs.illinois.edu, ppl AT cs.uiuc.edu
Subject: [charm] Processor slicing and miniaturising in BigSim
Date: Sun, 1 Jul 2018 21:48:47 +0530
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Respected sir/madam,

In the paper "Simulating Large Scale Parallel Applications using Statistical Models for Sequential Execution Blocks" Zheng et. al, (mentioned under research/BigSim in the charm website)

in page number (4) it is mentioned regarding processor slicing and miniaturising for the emulation.

Is it possible to provide more insight on these regarding what methodology has been adopted to achieve them?

Is there any way the user/ programmer can control those factors ?

Or is there any other ideas implemented to make the simulation faster?

Thank you,

Vishwas V.K.

[charm] Processor slicing and miniaturising in BigSim, vishwas vasudeva, 07/01/2018
- Re: [charm] Processor slicing and miniaturising in BigSim, Eric Bohm, 07/03/2018