Charm++ parallel programming system

[Eric Bohm <ebohm AT illinois.edu>]

Processor slicing is part of a multi pass process.

In the first pass, the entire target machine is emulated with coarse detail 
and an event trajectory is recorded (using the record replay feature) is made 
of the subset of processors that is the slice target.

The execution trace of the slice of processors is then replayed in a higher 
fidelity simulator.  The exact details vary depending on which aspects of the 
machine and application performance are of most interest.

> On Jul 1, 2018, at 11:18 AM, vishwas vasudeva 
> <vishvasu98 AT gmail.com>
>  wrote:
> 
> Respected sir/madam,
> 
> In the paper "Simulating Large Scale Parallel Applications using 
> Statistical Models for Sequential Execution Blocks" Zheng et. al, 
> (mentioned under research/BigSim in the charm website)
> in page number  (4)   it is mentioned regarding processor slicing and 
> miniaturising for the emulation.
> Is it possible to provide more insight on these regarding what methodology 
> has been adopted to achieve them?
> Is there any way the user/ programmer can control those factors ?
> Or is there any other ideas implemented to make the simulation faster?
> 
> Thank you,
> Vishwas V.K.